A Configuration Concept for a Massively Parallel FPGA Architecture
نویسندگان
چکیده
The emerging technology of programmable logic devices enables a new kind of architecture for massively parallel. For such systems the traditional way of chip configuration is not useful anymore. This paper presents a concept for configuring massively parallel reconfigurable architectures. Furthermore a proof of concept is given by applying the configuration scheme to an reconfigurable architecture consisting of 120 programmable logic devices.
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